Staff Physical Design Engineer
Company: Marvell Semiconductor, Inc.
Location: Santa Clara
Posted on: October 3, 2024
Job Description:
About Marvell Marvell's semiconductor solutions are the
essential building blocks of the data infrastructure that connects
our world. Across enterprise, cloud and AI, automotive, and carrier
architectures, our innovative technology is enabling new
possibilities.At Marvell, you can affect the arc of individual
lives, lift the trajectory of entire industries, and fuel the
transformative potential of tomorrow. For those looking to make
their mark on purposeful and enduring innovation, above and beyond
fleeting trends, Marvell is a place to thrive, learn, and lead.Your
Team, Your ImpactBuilt on decades of expertise and execution,
Marvell's custom Processor/ASIC solution offers a differentiated
approach with a best-in-class portfolio of data infrastructure
intellectual property (IP) and a wide array of flexible business
models. In this unique role, you'll have the opportunity to work on
both the physical design and methodology for future designs of our
next-generation, high-performance processor chips in a leading-edge
CMOS process technology, targeted at server, 5G/6G, automotive, and
networking applications.What You Can ExpectIn this hybrid role
based in Santa Clara, CA, you will work with a global team on both
the physical design of complex chips as well as the methodology to
enable an efficient and robust design process. You will be
responsible for maintaining, enhancing, and supporting Marvell's
Place and Route Flow, leveraging industry-standard EDA tools.
- Your tasks will include performing synthesis, place and route,
as well as timing analysis and closure on multiple intermediate and
complex logic blocks.
- You will play a crucial role in developing and implementing
timing and logic ECOs, collaborating closely with the RTL design
team to drive modifications that address congestion and timing
issues.
- Collaboration with the frontend team will be crucial to ensure
successful tapeouts. Additionally, your involvement with the global
timing team will include debugging and resolving any block-level
timing issues encountered at the partition level. This position
provides an exciting platform to engage with diverse engineering
challenges within a collaborative and innovative environment at
Marvell.What We're Looking For
- Have completed a Bachelor's OR a Master's Degree in
Electrical/Computer Engineering, Computer Science, or related
fields and have 3+ years of relevant industry experience in
physical design, with a focus on implementation. In your
coursework, you must have completed a digital logic course and
projects that involved circuit design, testing, and timing
analysis.
- Good understanding of standard RTL to GDS flows and
methodology, experience in designing ICs at advanced technology
nodes (e.g., 7nm, 5nm, or below) is desirable.
- Scripting skills in languages such as Perl, tcl, and
Python
- Good object-oriented programming skills
- Good understanding of digital logic and computer
architecture
- Knowledge of Verilog/VHDL
- Good communication skills and self-discipline contributing in a
team environment
- Knowledge and experience with industry-standard physical design
tools and methodologies, including synthesis, floor planning,
placement, clock tree synthesis, routing, and physical
verification.Expected Base Pay Range (USD)100,840 - 151,000, $ per
annumThe successful candidate's starting base pay will be
determined based on job-related skills, experience, qualifications,
work location and market conditions. The expected base pay range
for this role may be modified based on market conditions.Additional
Compensation and Benefit ElementsAt Marvell, we offer a total
compensation package with a base, bonus and equity.Health and
financial wellbeing are part of the package. That means flexible
time off, 401k, plus a year-end shutdown, floating holidays, paid
time off to volunteer. Have a question about our benefits packages
- health or financial? Ask your recruiter during the interview
process.This role is eligible for our hybrid work model in which
you will be able to split time between working from home and
on-site in a Marvell office.All qualified applicants will receive
consideration for employment without regard to race, color,
religion, sex, national origin, sexual orientation, gender
identity, disability or protected veteran status.Any applicant who
requires a reasonable accommodation during the selection process
should contact Marvell HR Helpdesk at .#LI-JS22
Keywords: Marvell Semiconductor, Inc., San Mateo , Staff Physical Design Engineer, Engineering , Santa Clara, California
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